Electrical busses require termination by resistors or impedance circuits to prevent signal reflections due to impedance mismatch between the bus line and any empty space beyond the end of the bus. Different bus topologies have different termination schemes. Some input/output (IO) busses may be terminated high (e.g., to supply voltage, VDD), and others may be terminated low (e.g., to ground). The increased processing power and requirements of present computing and communications systems has led to the development of high bandwidth memory devices and interfaces. One such standard is double data rate memory (DDR), such as GDDR-4 which terminates to VDD.
When current flows through a circuit, Direct Current (DC) power is consumed. It is generally desirable to reduce power consumption in many applications, and especially in mobile or miniaturized devices. In order to reduce the power consumption in bus-based circuits, it is desirable to maintain the bus in the particular logic state in which there is no current flow. The logic state in which there is no current flow depends upon the termination scheme of the bus. For example, a unipolar current-mode IO scheme consists of a switchable current source that, when active, pulls down on a termination resistor to generate the voltage sensed by the receiver. In a high termination system, DC power is consumed when the output is pulled down (logical 0), and no DC power is consumed (no current flows) when a logical one is transmitted. In a low termination system, the opposite is true; that is, no DC power is consumed for the logic 0 state, and DC power is consumed for logic 1 state.
In general, a bus must toggle to transmit data. FIG. 1 is a timing diagram illustrating the transmission of a data burst for an example bus circuit. Clock signal 102 represents a full-speed clock with a particular period, e.g., 1 ns. An example data burst 104 of eight bits 1 1 0 1 0 1 0 1 is transmitted in synchronization with the clock signal 102. Although one burst of eight bits is shown, it should be noted that any number of bits or data bursts can be transmitted in sequence. In an SDR (single data rate) system, as shown, each bit is transmitted on the rising edge of the clock signal. For clock periods in which no data is sent, the bus is in an idle state, as may be denoted by the presence of “D” symbols. For a DDR system, bits are transmitted on both the rising and falling edge of the clock signal. Although embodiments may be illustrated with respect to SDR systems, it should be noted that these embodiments also apply to DDR systems.
Present methods of reducing the DC power consumption during data transmission is data bus inversion, in which the sense of all of the bits on the bus is inverted if more than half will be pulled down. This technique can reduce the DC power nearly in half in certain applications. However, this approach typically requires the use of pins in a device (such as to indicate the inversion), and this in itself also consumes power.
Another technique of reducing DC power consumption, which is commonly used in current DRAM (dynamic random access memory) protocols, is to reduce the operating frequency of the bus. This approach is illustrated in FIG. 2, in which clock signal 202 switches at a lower frequency (longer period) than the full-speed clock signal 102, and the bits within data burst 204 are accordingly transmitted at a slower rate. For the example shown in FIG. 1B, clock signal 202 is approximately one-quarter the frequency of clock signal 102. This approach may reduce unnecessary switching in the control logic and thus save power, however, the energy per transition remains constant. This approach also requires the determination of the minimum frequency required to maintain the required bandwidth. Another disadvantage associated with this approach is that it does not ensure that the bus will remain in the logic state that minimizes current flow for a majority of the time.